Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit to facilitate the process of Read Out Secured Heximal of Microprocessor dsPIC30F6010A, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
To set up a Synchronous Master Reception:
- Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate.
3. Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set.
- Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception.
- Read the 8-bit received data by reading the RCREG register.
- If any error occurred, clear the error by clearing bit CREN.
- If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode) to Read Out Secured Heximal of Microprocessor dsPIC30F6010A. This allows the device to transfer or receive data while in any low-power mode. The operation of the Synchronous Master and Slave modes are identical, except in the case of the Sleep mode.
If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur:
The first word will immediately transfer to the TSR register and transmit.
The second word will remain in the TXREG register.
Flag bit, TXIF, will not be set.
When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set.
To set up a Synchronous Slave Transmission:
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit TXEN.
If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.
Start transmission by loading data to the TXREGx register.
If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
