We can Read Chip TS87C54X2 Eeprom, please view the Chip TS87C54X2 features for your reference:

The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H when Read Chip
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• HDW Watchdog Timer Reset: WDTRST, WDTPRG
• Interrupt system registers: IE, IP, IPH
• Others: AUXR, CKCON if Read ChipIn comparison to the original 80C52, the TS80C54/58X2 implements some new features, which are:
  • The X2 option.
  • The Dual Data Pointer.
  • The Watchdog.
  • The 4 level interrupt priority system before Read Chip.
  • The power-off flag.
  • The ONCE mode.
  • The ALE disabling.
  • Some enhanced features are also located in the UART and the timer 2 after Read Chip.The TS80C54/58X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides thefollowing advantages:Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

    Save power consumption while keeping same CPU power (oscillator power saving) when Read Chip.

    Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.

    Increase CPU power by 2 while keeping same crystal frequency.
    In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main

    clock input of the core (phase generator). This divider may be disabled by software if Read Chip.

    The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1 before Read Chip. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.

    Figure 2. shows the mode switching waveforms.

  • The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) after Read Chip.