Read Chip PIC16LF876A Flash and eeprom program or data out from the memory by using focus ion beam technique through microcontroller unlocking, the status of MCU will be reset from locked to unlocked one;

The Power Control/Status Register, PCON, has two bits to indicate the type of RESET that last occurred. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset.

It must then be set by the user and checked on subsequent RESETS to see if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable.

Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.

The PIC16F7X family has up to 12 sources of interrupt. The interrupt control register (INTCON) records individ- ual interrupt requests in flag bits. It also has individual and global interrupt enable bits after extract chip embedded firmware.

A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled and an interrupt’s flag bit and mask bit are set, the interrupt will vector immediately.

Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on RESET if chip binary extraction.

The “return from interrupt” instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.