Microchip PIC18LF452 Microprocessor Firmware Extraction can disable the security fuse bit and then crack MCU protective mechanism for copy the firmware into flash and eeprom memory;

1. ADC gain stage output range is limited to 2.6 V.
The amplified output of the ADC gain stage will never go above 2.6V, hence the differential input will only give correct output when below 2.6V/gain. For the available gain settings, this gives a differential input range of:
– 1X gain: 2.6V
– 2X gain: 1.3V
– 4X gain: 0.65V
– 8X gain: 325 mV
– 16X gain: 163 mV
– 32X gain: 82 mV
– 64X gain: 41 mV
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.6V in order to get a correct result, or keep ADC voltage reference is below2.6V when extract firmware from microprocessor.

The ADC has up to ±2 LSB inaccuracy

The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input voltage/ output value transfer function of the ADC. The inaccuracy increases with increasing voltage reference reaching ±2 LSB with 3V reference.

Problem fix/Workaround

None, the actual ADC resolution will be reduced with up to ±2 LSB.

TWI, a general address call will match independent of the R/W-bit value. When the TWI is in Slave mode and a general address call is issued on the bus, the TWI Slave will get an address match regardless of the R/W-bit (ADDR[0] bit) value in the Slave Address Register if the microprocessor’s firmware can be extracted.

Problem fix/Workaround

Use software to check the R/W-bit on general call address match.

TWI, the minimum I2C SCL low time could be violated in Master Read mode

When the TWI is in Master Read mode and issuing a Repeated Start on the bus, this will immediately release the SCL line even if one complete SCL low period has not passed. This means that the minimum SCL low time in the I2C specification could be violated.

Problem fix/Workaround

If this causes a potential problem in the application, software must ensure that the Repeated Start is never issued before one SCL low time has passed.

Setting HIRES PR bit makes PWM output unavailable

Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM output for the corresponding Timer/Counters (TCx0 and TCx1) unavailable on the pin before firmware of microprocessor has been extracted.

Problem fix/Workaround

Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is used.

EEPROM erase and write does not work with all System Clock sources

When doing EEPROM erase or Write operations with other clock sources than the 2 MHz RCOSC, Flash will be read wrongly for one or two clock cycles at the end of the EEPROM operation.

Problem fix/Workaround

Alt 1: Use the internal 2 MHz RCOSC when doing erase or write operations on EEPROM.

Alt 2: Ensure to be in sleep mode while completing erase or write on EEPROM. After starting erase or write operations on EEPROM, other interrupts should be disabled and the device put to sleep after the extract of microprocessor firmware had been completed.