A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted to proceed with Locked Microcontroller dsPIC30F6012 Heximal Copying. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O.
The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module.
The value in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, After this acquisition time has elapsed, the A/D conversion can be started to Locked Microcontroller dsPIC30F6012 Heximal Copying. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion.
The following steps should be followed to perform an A/D conversion:
Configure the A/D module:
• Configure analog pins, voltage reference and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0) Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0 register);
Wait for A/D conversion to complete, by either:
- Polling for the GO/DONE bit to be cleared OR
- Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
