We can Extract Microchip PIC16LF690 Program, please view the Microchip PIC16LF690 features for your reference:

That is:

• SDI is automatically controlled by the SPI module
• SDO must have TRISC<7> bit cleared
• SCK (Master mode) must have TRISB<6> bit cleared

• SCK (Slave mode) must have TRISB<6> bit set when extract microchip program
• SS must have TRISC<6> bit set

Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRISB and TRISC) registers to the opposite value.

Figure 13-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal after microchip program extraction.

Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time if extract microchip program.

Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission:

• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data of microchip program The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 13-2) is to broadcast data by the software protocol extraction. In Master mode, the data is transmitted/received as  soon as the SSPBUF register is written to carry out IC Cloning.
• If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate of microchip program. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and Status bits appropriately set). This could be useful in receiver applications as a Line Activity Monitor mode.The clock polarity is selected by appropriately programming the CKP bit of the SSPCON register. This then, would give waveforms for SPI communication of extraction as shown in Figure 13-3, Figure 13-5 and Figure 13-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following:

  FOSC/4 (or TCY)

  FOSC/16 (or 4 · TCY)
  FOSC/64 (or 16 · TCY)
  Timer2 output/2 (PIC16F685/PIC16F690 only) if extract microchip program
• This allows a maximum data rate (at 40 MHz) of 10 Mbps.
  Figure 13-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown after extract microchip program.