Extract MCU AT89LV55 Code from its memory needs to unlock microcontroller secured mechanism and then dump the firmware, the process will start from decapsulate the silicon package of MCU;
In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset when Extract MCU at89c52 heximal.
Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly.
The AT89LV55 code memory array is programmed byte-by-byte. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. The AT89LV55 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.
Programming Algorithm: Before programming the AT89LV55, the address, data and control signals should be set up according to the Flash programming mode table and Figure 9 and Figure 10. To program the AT89LV55, take the following steps:
- Input the desired memory location on the address lines
- Input the appropriate data byte on the data lines.
- Activate the correct combination of control signals.
- Pulse ALE/PROG once to program a byte in the FlashRaise EA/VPP to 12V array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps if Extract chip embedded firmware
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1 through 5, changing the address and data for the entire array or until the end of the object file is reached.
Data Polling: The AT89LV55 features Data Polling to indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the complement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BUSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase: The entire Flash array is erased electrically by using the prope r combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all 1s. The chip erase operation must be executed before the code memory can be reprogrammed.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, and 031H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:
(030H) = 1EH indicates manufactured by Atmel
(031H) = 65H indicates 89LV55
(032H) = FFH indicates 12V programming
Every code byte in the Flash array can be written, and the entire array can be erased, by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion.
All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.
