The XMEGA A1 devices contains On-chip In-System Programmable Flash memory for Extract Heximal of MCU ATXMEGA64A3. Since all AVR instructions are 16- or 32-bits wide, each Flash address location is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both sections have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Program Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash memory.
A third section inside the Application section is referred to as the Application Table section which has separate Lock bits for storage of write or read/write protection.
The Application Table section can be used for storing non-volatile data or application software.The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one linear address space.
To simplify development, the memory map for all devices in the family is identical and with empty, reserved memory space for smaller devices.All peripherals and modules are addressable through I/O memory locations in the data memory space.
All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 – 0x3F directly. I/O registers within the address range 0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Peripheral Module Address Map”.
The XMEGA A1 devices has internal EEPROM memory for non-volatile data storage. It is addressable either in a separate data space or it can be memory mapped into the normal data memory space. The EEPROM memory supports both byte and page access.
Supports SRAM up to
– 512K Bytes using 2-port EBI
– 16M Bytes using 3-port EBI
Supports SDRAM up to
– 128M bit using 3-port EBI
Four software configurable Chip Selects
Software configurable Wait State insertion
Clocked from the Peripheral 2x Clock at up to two times the CPU clock speed
