In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value when Extract Flash from Microprocessor PIC16LF873. When a match occurs, the RC5/T1CKI/CCP1/SEG10 pin is:
Driven high
Driven low
Remains unchanged
The action on the pin is based on the value of control bits CCP1M<3:0> (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. The user must configure the RC5/T1CKI/CCP1/SEG10 pin as an output by clearing the TRISC<5> bit from Copy Chip PIC16F767 Program.
Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work when unlock Microcontroller. When Generate Software Interrupt mode is chosen, the RC5/T1CKI/CCP1/SEG10 pin is not affected. The CCPIF bit is set, causing a CCP interrupt (if enabled).
In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1.
The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the RC5/T1CKI/CCP1/SEG10 pin is multiplexed with the PORTC data latch, the TRISC<5> bit must be cleared to make the RC5/T1CKI/CCP1/SEG10 pin an output.
For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 15.3.3 “Setup for PWM Operation”. A PWM output has a time base (period) and a time that the output stays high (duty cycle) by Reading Microcontroller PIC16F777 Heximal. The frequency of the PWM is the inverse of the period (1/period).
When TMR2 is equal to PR2, the following three events occur on the next increment cycle:
TMR2 is cleared
The RC5/T1CKI/CCP1/SEG10 pin is set (exception: if PWM duty cycle = 0%, the RC5/T1CKI/CCP1/SEG10 pin will not be set)
The PWM duty cycle is latched from CCPR1L into CCPR1H
