Extract Embedded Firmware from Chip PIC18F4420 which include the flash and eeprom memory, once the status of Microcontroller PIC18F4420 has been reset from locked to unlocked version by MCU cracking;
The PIC18F4420 devices differentiate between various kinds of Reset:
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power managed modes
Watchdog Timer (WDT) Reset (during execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.2.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 23.2 “Watchdog Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1.
Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 “Reset State of Registers” if the program of microcontroller can be extracted.
The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 9.0 “Interrupts”. BOR is covered in Section 4.4 “Brown-out Reset (BOR)”. The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses.
The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F4420 devices, the MCLR input can be disabled with the MCLRE configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.5 “PORTE, TRISE and LATE Registers” for more information.
