The overall structure of the code protection on the SN8P2234 Flash devices differs significantly from other
SN8P2234 devices. The user program memory is divided into five blocks which has increase the difficulty of Extract Code of Locked MCU SN8P2234. One of these is a boot block of 2 Kbytes. The remainder of the memory is divided into four blocks on binary boundaries.Each of the five blocks has three code protection bits associated with them. They are:

• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)

Figure 23-5 shows the program memory organization for 16 and 32-Kbyte devices and the specific code protection bit associated with each block. The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions when extract firmware of chip.

In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is ‘0’. The EBTRn bits control  table reads. For a block of user memory with the EBTRn bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. A table read instruc-tion that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s if extract data from mcu.

Figures 23-6 through 23-8 illustrate table write and table read protection.

Code protection bits may only be written to a ‘0’ from a ‘1’ state. It is not possible to write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer.

The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM which will hinder the process of Extract Code of Locked MCU SN8P2234. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings.

The configuration registers can be write-protected. The WRTC bit controls protection of the configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer.