Encrypted Microprocessor PIC18F4682 Code Extraction starts from cracking MCU memory include flash and eeprom, after this process the status of Microcontroller will reset from encrypted to decryption and code will be dump from it;
In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT).
Table read operations retrieve data from program memory and places it into the data RAM space.
Figure 6-1 shows the operation of a table read with program memory and data RAM.
Table write operations store data from the data memory space into holding registers in program memory. The
procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the operation of a table write with program memory and data
RAM when copy hex from PIC16F871.
Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned if microcontroller pic16lf871’s code can be extracted.
The EECON1 register (Register 6-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. The CFGS control bit determines if the access will be to the configuration/calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on configuration registers regardless of EEPGD (see Section 23.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD.
