The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode to Embedded Firmware Extract of Locked MCU dsPIC30F6011. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from the low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC.
If interrupts are desired, set enable bit RCIE
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit, RCIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCIE, was set.
Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception.
Read the 8-bit received data by reading the RCREG register.
If any error occurred, clear the error by clearing bit CREN.
If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
The Analog-to-Digital (A/D) converter module has 10 inputs for the 28-pin devices and 13 for the 40/44-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.
The module has five registers:
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 19-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 19-2, configures the functions of the port pins to carry out the Embedded Firmware Extract of Locked MCU dsPIC30F6011. The ADCON2 register, shown in Register 19-3, configures the A/D clock source, programmed acquisition time and justification.
The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode.
To operate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation.
