Copy Software of Locked MCU PIC18F6310 from its flash and eeprom memory, copy the firmware to new Microontroller PIC18F6310 for the perfect cloning, the status of Microcontroller will be reset from locked to unlocked version;

The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored when read microchip mcu pic16f876 program.

The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.

The sequence of events for erasing a block of internal program memory location is: Load Table Pointer register with address of row being erased.

Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.

Disable interrupts.

Write 55h to EECON2.

Write 0AAh to EECON2.

Set the WR bit. This will begin the row erase cycle.

The CPU will stall for duration of the erase (about 2 ms using internal timer).

Re-enable interrupts.

The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write.