Copy Secured Microcomputer dsPIC30F6014A Embedded Binary

The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits to Copy Secured Microcomputer dsPIC30F6014A Embedded Binary, as read from CMCON<7:6>, to determine the actual change that occurred.

The CMIF bit (PIR2<6>) is the Comparator Interrupt Flag. The CMIF bit must be reset by clearing it. Since it is also possible to write a ‘1’ to this register, a simulated interrupt may be initiated.

Copy Secured Microcomputer dsPIC30F6014A Embedded Binary
Copy Secured Microcomputer dsPIC30F6014A Embedded Binary

Both the CMIE bit (PIE2<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. Inaddition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the interrupt in the following manner:

Any read or write of CMCON will end the mismatch condition.

Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared.

When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode, when enabled.

Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators (CM2:CM0 = 111) before entering Sleep. If the device wakes up from Sleep when Copy Secured Microcomputer dsPIC30F6014A Embedded Binary, the contents of the CMCON register are not affected.

A device Reset forces the CMCON register to its Reset state, causing the comparator modules to be turned off (CM2:CM0 = 111). However, the input pins (RA0 through RA3) are configured as analog inputs by default on device Reset. The I/O configuration for these pins is determined by the setting of the PCFG3:PCFG0 bits (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset time.