The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs in the end of Locked Microcomputer DsPIC30F4012 Program copying. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time:

CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitch-free PWM operation after Microcontroller Unlocking. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the formula:

SETUP FOR PWM OPERATION

The following steps should be taken when configuring the CCP module for PWM operation: Set the PWM period by writing to the PR2 register to facilitate the process of Encrypted Microcontroller DsPIC30F4011 source code extraction.

Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the RC5/T1CKI/CCP1/SEG10 pin an output by clearing the TRISC<5> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.