The register file is organized as 256 x 8 in the PIC16F917 and 352 x 8 in the PIC16F917. Each register is accessed either directly or indirectly through the File Select Register (FSR) which is critical for Copy Microchip MCU PIC16LF917 Heximal (see Section 2.5 “Indirect Addressing, INDF and FSR Registers”).

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device. These registers are static RAM.

The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

The Status register, shown in Register 2-1, contains:

• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)

The Status register can be the destination for any instruction, like any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled.

These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the Status register as destination may be different than intended.

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Status register, because these instructions do not affect any Status bits from Copy Microchip MCU PIC16LF917 Heximal. For other instructions not affecting any Status bits (see Section 17.0 “Instruction Set Summary”) .

The INTCON register of PIC16F917 is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RB0/INT/SEG0 pin interrupts.