We can Copy Chip PIC16C74B Flash, please view the Chip PIC16C74B features for your reference:

Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will
take precedence when copy chip flash.
In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1. TMR1H and TMR1L registers are not reset to 00h on a POR, or any other Reset, except by the CCP1 and CCP2 special event triggers from chip flash.

T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other Resets, the register is unaffected.Timer1 can only operate during Sleep when setup in Asynchronous Counter mode before flash copying.

In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit (INTCON<7>) is set, the device will wake-up and jump to the Interrupt Service Routine (0004h) on an overflow after chip flash being copied.
If the GIE bit is clear, execution will continue with the next instruction. The Timer2 module timer has the following features:

8-bit timer (TMR2 register)

8-bit period register (PR2)

Readable and writable (both registers)

Software programmable prescaler (1:1, 1:4, 1:16)

Software programmable postscaler (1:1 to 1:16)

Interrupt on TMR2 match with PR2

Timer2 has a control register shown in Register 7-1.

TMR2 can be shut-off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption before copy flash from chip.

Figure 7-1 is a simplified block diagram of the Timer2 module. The prescaler and postscaler selection of Timer2 are controlled by this register.

Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPSx (T2CON<1:0>) after copy chip flash.

The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).

The prescaler and postscaler counters are cleared when any of the following occurs:

• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written when copy flash chip.