The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO for Extract PIC16F1782 MCU Source Code. The RCIF interrupt flag bit is read-only when Unlock Microcontroller Flash, it cannot be set or cleared by software.

RCIF interrupts are enabled by setting all of the following bits:

RCIE Interrupt Enable bit of the PIE1 register

PEIE Peripheral Interrupt Enable bit of the INTCON register

GIE Global Interrupt Enable bit of the INTCON register

The RCIF interrupt flag bit will be set when there is an unread character in the FIFO when Read Microcontroller PIC16F1704 Eeprom Heximal, regardless of the state of interrupt enable bits.

Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time for the purpose of Extract Microchip PIC16F1703 Program Heximal. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.

The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters in order to Dump PIC16F1527 Microcontroller Source Code. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit by Break MCU PIC16F1526 Internal Memory Flash. A framing error by itself does not generate an interrupt.

NOTE: If all receive characters  in  the  receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit.