We can Read Microchip Processor PIC18F6585 Data, please view the Microchip Processor PIC18F6585 features for your reference:

Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA.

Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in the Configuration register (see Section 19.1 “Configuration Bits” for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’ when Read Microchip Processor PIC18F6585 Data.

The RA0 pin is multiplexed with one of the analog inputs, one of the external interrupt inputs, one of the interrupt-on-change inputs and one of the analog comparator inputs to become RA0/AN0/INT0/KBI0/CMP0 pin.

The RA1 pin is multiplexed with one of the analog inputs, one of the external interrupt inputs and one of the interrupt-on-change inputs to become RA1/AN1/INT1/KBI1 pin. Pins RA2 and RA3 are multiplexed with the Enhanced USART transmission and reception input (see Section 19.1 “Configuration Bits” for details) after Read Microchip Processor PIC18F6585 Data.

The RA4 pin is multiplexed with the Timer0 module clock input, one of the analog inputs and the analog VREF+ input to become the RA4/T0CKI/AN2/VREF+ pin. The Fault detect input for PWM FLTA is multiplexed with pins RA5 and RA7. Its placement is decided by clearing or setting the FLTAMX bit of Configuration Register 3H.

On a Power-on Reset, RA0, RA1, RA4 and RA5 are configured as analog inputs and read as ‘0’. RA2 and RA3 are configured as digital inputs when READ MCU.