We can Read Out Microcontroller PIC18F6310 Eeprom Memory, please view the Microcontroller PIC18F6310 features for your reference:

If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed, if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed.

The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR) when Read Out Microcontroller PIC18F6310 Eeprom Memory.

There are four SFRs used to read and write the program and data EEPROM memory. These registers are:

EECON1

EECON2

EEDATA

EEADR

The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed.

These devices have 128 bytes of data EEPROM with an address range from 00h to FFh.

The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to parameter D122 (Table 22-1 in Section 22.0 “Electrical Characteristics”) for exact limits after Read Out Microcontroller PIC18F6310 Eeprom Memory.

The EEPROM Address register can address 256 bytes of data EEPROM. EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences.

Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear,  operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory.

When set, subsequent operations access Configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory before Read MCU.