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When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation when Extract Microprocessor PIC18F4680 Embedded Code.

For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.

The sequence of events for erasing a block of internal program memory location is:

Load Table Pointer register with address of row being erased.

Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase after Extract Microprocessor PIC18F4680 Embedded Code.

Disable interrupts.

Write 55h to EECON2.

Write 0AAh to EECON2.

Set the WR bit. This will begin the row erase cycle.

The CPU will stall for duration of the erase (about 2 ms using internal timer).

Re-enable interrupts before READ MCU.