We can Extract Locked Microcontroller PIC18F4610 Heximal, please view the Microcontroller PIC18F4610 features for your reference:
The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete.
During normal operation, the WRERR may read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation when Extract Locked Microcontroller PIC18F4610 Heximal.
The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM.
The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the Configuration bits if Extract Locked Microcontroller PIC18F4610 Heximal.
The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in
Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits.
