To use a higher clock speed on wake-up, the INTOSC or To use a higher clock speed on wake-up, the INTOSC orpostscaler clock sources can be selected to provide a higher clock speed by setting bits which will be benefit for Copy Content of MCU SN8P2213 EEPROM, IRCF2:IRCF0, immedi-ately after Reset.

For wake-ups from Sleep, the INTOSCor postscaler clock sources can be selected by setting theIRCF2:IRCF0 bits prior to entering Sleep mode.The FSCM will detect failures of the primary or second-ary clock sources only. If the internal oscillator blockfails, no failure would be detected, nor would any actionbe possible.

Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected.

Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset.

For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out after the completeness of Copy Content of MCU SN8P2213 EEPROM.  The fail-safe condition is terminated by either a device Reset or by entering a power managed mode.

On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the device clock until the primary clock source becomes ready when Copy Content of MCU SN8P2213 EEPROM(similar to a Two-Speed Start-up).

The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power managed mode is entered.