Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D conversion sample by Copy Secured Program of Microprocessor dsPIC30F6013A. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. The discharge phase is used to initialize the value of the capacitor array.
The array is discharged before every sample. This feature helps to optimize the unity gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values.An A/D conversion can be started by the Special Event Trigger of the CCP2 module.
This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input chan-nel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3) counter. The analog comparator module contains two comparators that can be configured in a variety of ways for Copy Secured Program of Microprocessor dsPIC30F6013A.
The inputs can be selected from the analog inputs multiplexed with pins RA0 through RA5, as well as the on-chip voltage reference (see Section 21.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register.The CMCON register (Register 20-1) selects the comparator input and output configuration. Block diagrams of the various comparator configurations.
