This mode would typically be used in RS-485 systems which is a critical part for the process of Read Out Software of MCU Processor dsPIC30F5015. To set up an Asynchronous Reception with Address Detect Enable:
Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate.
Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit.
If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable).
Read RCREG to determine if the device is being addressed. If any error occurred, clear the CREN bit.
If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed.
The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>). Once set before Read Out Software of MCU Processor dsPIC30F5015, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode.
A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.).
Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 18-8) and asynchronously, if the device is in Sleep mode (Figure 18-9). The interrupt condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-high transition is observed on the RX line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over.
