We can Read Data of Locked Microprocessor PIC10F204, please view the Microprocessor PIC10F204 features for your reference:

The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected:
• I2C Master mode, clock = (FOSC/4) x (SSPADD + 1)
• I 2C Slave mode (7-bit address)•
I 2C Slave mode (10-bit address)

I 2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled

• I 2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled
• I 2C Firmware Controlled Master mode, slave is Idle

Selection of any I 2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins.

In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I 2C Slave mode hardware will always generate an interrupt on an address match to unlock microcontroller. Through the mode select bits, the user can also choose to interrupt on Start and Stop bits When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register.

Any combination of the following conditions will cause the MSSP module not to give this ACK pulse:

• The Buffer Full bit, BF (SSPSTAT<0>), was set before the transfer was received.
• The overflow bit, SSPOV (SSPCON<6>), was set before the transfer was received.

In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101.