Protected Chip PIC18F6525 Heximal Reading

Protected Chip PIC18F6525 Heximal Reading from its flash and eeprom memory, then duplicate the content to new Microontroller PIC18F6525 for the exact replication and the MCU will provide the same functions as originals IC Clone;

Protected Chip PIC18F6525 Heximal Reading from its flash and eeprom memory
Protected Chip PIC18F6525 Heximal Reading from its flash and eeprom memory

The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers when read hex from MCU PIC16F628.

When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory.

EECON1

EECON2

EEDATA

The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. The WR control bit initiates write operations. The bit can be set but not cleared in software. It is only cleared in hardware at the completion of the write operation. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation if the microchip PIC16F627 firmware can be extracted.

The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).