When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation of Read Heximal from Microcontroller PIC12LC672. If these conditions are not met, the device must be held in Reset until the operating conditions are met.
For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607).
PIC12LC672 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from early devices of this family after Crack MCU.
Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD in order to Extract Protected MCU PIC16F884 Heximal. The use of an RC network, as shown in Figure 16-2, is suggested.
An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When cleared, MCLR is internally tied to VDD and an internal weak pull-up is enabled for the MCLR pin. In-Circuit Serial Programming is not affected by selecting the internal MCLR option after Read Heximal from Microcontroller PIC12LC672.
The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 4.4 “Internal Clock Modes”. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level for the purpose of Extract Microcontroller PIC16F883 File. A configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip and vary due to:
VDD variation
Temperature variation
Process variation
See DC parameters for details
