Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution in the process of Copy Encrypted AVR MCU PIC16C621A. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device.
This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable.
the Oscillator Start-up Timer (OST) is enabled (see Section 4.3.1 “Oscillator Start-up Timer (OST)”). The OST timer will suspend program execution until 1024 oscillations are counted.
Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit (OSCCON<3>) is set, program execution switches to the external oscillator.
Two-Speed Start-up mode is configured by the following settings:
- IESO = 1 (CONFIG<10>) Internal/External Switchover bit.
- SCS = 0.
- FOSC configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after:
- Wake-up from Sleep.
If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep.
The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate in the event of an oscillator failure. The FSCM can detect oscillator failure at any point after the device has exited a Reset or Sleep condition and the Oscillator Start-up Timer (OST) has expired.
The FSCM function is enabled by setting the FCMEN bit in the Configuration Word (CONFIG). It is applicable to all external clock options after Copy Encrypted AVR MCU PIC16C621A (LP, XT, HS, EC or RC modes).
In the event of an external clock failure, the FSCM will set the OSFIF bit (PIR2<7>) and generate an oscillator fail interrupt if the OSFIE bit (PIE2<7>) is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited.
