The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered approximately ±12% via software using the OSCTUNE register (Register 4-2) when Copy Locked PIC16C65B Program.

The output of the HFINTOSC connects to a postscaler and multiplexer. One of seven frequencies can be selected via software using the IRCF bits (see Section 4.4.4 “Frequency Select Bits (IRCF)”). The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz (IRCF ≠ 000) as the System Clock Source (SCS = 1), or when Two-Speed Start-up is enabled (IESO = 1 and IRCF ≠ 000).

The HF Internal Oscillator (HTS) bit (OSCCON<2>) indicates whether the HFINTOSC is stable or not. The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). The OSCTUNE register has a tuning range of ±12%. The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. Due to process variation, the monotonicity and frequency step cannot be specified.

When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. The HFINTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred.

OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency which will faciliate the process of Copy Locked PIC16C65B Program.

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 4-1). 31 kHz can be selected via software using the IRCF bits (see Section 4.4.4 “Frequency Select Bits (IRCF)”).

The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF = 000) as the System Clock Source (SCS = 1), or when any of the following are enabled:

Two-Speed Start-up (IESO = 1 and IRCF = 000)

Power-up Timer (PWRT)

Watchdog Timer (WDT)

Fail-Safe Clock Monitor (FSCM)

Selected as LCD module clock source

The LF Internal Oscillator (LTS) bit (OSCCON<1>) indicates whether the LFINTOSC is stable or not.