This section contains register definitions and operational characteristics of the SPI module which is critical for Microchip MCU PIC16F870 Heximal Extraction. Additional information on the SPI module can be found in the “PICmicro® Mid-Range MCU Family Reference Manual” (DS33023).

The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used:
• Serial Data Out (SDO) – RC4/T1G/SDO/SEG11
• Serial Data In (SDI) – RC7/RX/DT/SDI/SDA/SEG8
• Serial Clock (SCK) – RC6/TX/CK/SCK/SCL/SEG9
Additionally, a fourth pin may be used when in a Slave mode of operation:
• Slave Select (SS) – RA5/AN4/C2OUT/SS/SEG5
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6> to facilitate the process of Protected MCU PIC18F2610 code extraction. These control bits allow the following to be specified:

Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock edge (output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)

SMP: SPI™ Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode I2C™ mode:
This bit must be maintained clear
CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK (Microwire alternate)
SPI mode, CKP = 1:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK (Microwire default)
I2C mode:
This bit must be maintained clear
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last in order to Copy Binary From Protected MCU PIC18F2553.

SSPEN is cleared.
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
S: Start bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
SSPEN is cleared.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
R/W: Read/Write bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match to Crack MCU flash. This bit is only valid from the address match to the next Start bit, Stop bit or ACK bit
1 = Read
0 = Write