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Certain exits from power-managed modes do not invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source is not stopped; and
• the primary clock source is not any of the LP, XT, HS or HSPLL modes.
In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay when Dump Secured Microchip PIC18F4221 Heximal.
The PIC18F4221 devices differentiate between various kinds of Reset:
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during execution)
Programmable Brown-out Reset (BOR)
- f) RESET Instruction
- g) Stack Full Reset
- h) Stack Underflow Reset
This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.2.4 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 19.2 “Watchdog Timer (WDT)” after Dump Secured Microchip PIC18F4221 Heximal.
Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event from COPY MICROCONTROLLER.
